1. Field of the Invention
The present invention relates to systems and methods for testing integrated circuits. More particularly, the present invention is a system and method for determining an internal clock cycle at which a fault dependent upon operating conditions initially occurred.
2. Description of the Background Art
Integrated circuits are designed to properly function within particular ranges of operating or environmental conditions. Such conditions may include temperature; power supply voltage; input signal voltage levels; output signal loading; and/or other conditions. Integrated circuit manufacturers attempt to provide circuits that properly function within specified operating condition ranges, as well as outside such ranges.
Due to design and/or manufacturing flaws, one or more components within an integrated circuit may fail to exhibit acceptable functionality within a required operating condition range. As a result, an integrated circuit is subjected to tests during and/or after manufacture to determine whether it exhibits acceptable functionality. Such tests typically involve the application of test patterns to the integrated circuit at environmental extremes, and verifying whether the integrated circuit generates correct output responses.
Modern integrated circuits commonly include on the order of ten million transistors, essentially all of which must perform adequately over required ranges of operating conditions. Future integrated circuits are likely to include even greater numbers of transistors. Establishing which transistors within an integrated circuit are responsible for producing an observed failure can be very difficult.
Once an incorrect logic state exists within an integrated circuit, the incorrect logic state may not become observable at the integrated circuit's outputs for hundreds or even thousands of clock cycles. Furthermore, once conditions that activate an original fault or incorrect logic state are met, additional faults may occur prior to observation of the original fault. The additional faults may widen the divergence between correct and malfunctioning behavior, and/or obscure or cancel the effect of the original fault for a given amount of time in response to the application of certain test patterns.
What is needed is a system and method for reliably determining an exact clock cycle at which an incorrect internal logic state was first created, and minimizing any divergence between acceptable and faulty operation following creation of such a logic state.